The shrinkage of semiconductor devices increases a need for highly flat semiconductor wafers used as their substrate with improved productivity. In such circumstances, double-side polishing has been used for polishing wafers instead of conventional single-side polishing because of higher precision.
FIG. 8 shows a schematic diagram of a common double-side polishing apparatus of a planetary gear type. The double-side polishing apparatus 101 includes upper and lower turn tables. The upper turn table is movable upward and downward and can apply a load against a wafer interposed between the upper and lower turn tables by pressing the lower turn table. As shown in FIG. 8, the double-side polishing apparatus 101 includes a sun gear 107 disposed inside the lower turn table and an internal gear 108 disposed outside the lower turn table.
A carrier 105 to hold the wafer is disposed between the upper and lower turn tables, and can rotate with its outer circumference engaged with the sun gear 107 and the internal gear 108. The carrier 105 is rotated and revolved between the upper and lower turn tables according to the rotational speed of the sun gear 107 and the internal gear 108. The wafer, which is a subject to be polished, is inserted into a holding hole 106 formed in the carrier and held, so the wafer can be polished without coming off from the double-side polishing apparatus.
With regard to the planetary gear type of double-side polishing apparatus, it has been known that because the relation between the thickness of a carrier and the thickness of a polished wafer, a wafer finishing thickness, affects the flatness of the polished wafer, the flatness is controlled by adjusting the ratio of the finishing thickness to the thickness of the carrier (See Patent Document 1, for example).
In general, an improvement of the precision of flatness needs a decrease in polishing rate; an improvement of the productivity needs an increase in polishing rate. The polishing process is accordingly divided into two steps of a first polishing step and a second polishing step. The first polishing step performs rough polishing at a high polishing rate; the second polishing step performs precise polishing at a low polishing rate. In other words, the first polishing step contributes efficient polishing and the second polishing step contributes the achievement of precise flatness, so the flatness can be improved without reducing the productivity.
The finishing thickness is adjusted by changing the polishing time in the first polishing step. The above conventional method needs to finish a wafer with the optimal thickness depending on the carrier thickness to polish the wafer into a flat wafer.